2005 Microchip Technology Inc.
Preliminary
DS41265A-page 185
PIC16F946
15.1
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC5/T1CKI/CCP1/SEG10. An event is defined
as one of the following:
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
The type of event is configured by control bits
CCP1M<3:0> (CCPxCON<3:0>). When a capture is
made, the interrupt request flag bit CCP1IF (PIR1<2>)
is set. The interrupt flag must be cleared in software. If
another capture occurs before the value in register
CCPR1 is read, the old captured value is overwritten by
the new value.
15.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC5/T1CKI/CCP1/SEG10 pin
should be configured as an input by setting the
TRISC<5> bit.
FIGURE 15-3:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
15.1.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
15.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF, following any such
change in Operating mode.
15.1.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M<3:0>. Whenever the CCP module is turned
off, or the CCP module is not in Capture mode, the
prescaler counter is cleared. Any Reset will clear the
prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 15-1 shows the recom-
mended method for switching between capture pre-
scalers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 15-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
Note:
If the RC5/T1CKI/CCP1/SEG10 pin is
configured as an output, a write to the port
can cause a capture condition.
CCPR1H
CCPR1L
TMR1H
TMR1L
Set Flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Qs
CCP1CON<3:0>
RC5/T1CKI/
Prescaler
÷ 1, 4, 16
and
edge detect
pin
CCP1/SEG10
CLRF
CCP1CON
; Turn CCP module off
MOVLW
NEW_CAPT_PS ; Load the W reg with
; the new prescaler
; move value and CCP ON
MOVWF
CCP1CON
; Load CCP1CON with this
; value
相关PDF资料
2-1546217-0 TERM BLK RCPT 20POS SIDE 5.08MM
1-1546217-9 TERM BLK RCPT 19POS SIDE 5.08MM
1-1546217-8 TERM BLK RCPT 18POS SIDE 5.08MM
1-1546217-7 TERM BLK RCPT 17POS SIDE 5.08MM
1-1546217-6 TERM BLK RCPT 16POS SIDE 5.08MM
1-1546217-5 TERM BLK RCPT 15POS SIDE 5.08MM
1-1546217-4 TERM BLK RCPT 14POS SIDE 5.08MM
1-1546217-3 TERM BLK RCPT 13POS SIDE 5.08MM
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